datasheet pci-express clock source ics557-03 idt? / ics? pci-express clock source 1 ics557-03 rev l 022608 description the ics557-03 is a spread spectrum clock generator that supports pci-express and ethernet requirements. the device is used for pc or embe dded systems to substantially reduce electromagnetic interference (emi). the device provides two differential (hcsl) spread spectrum outputs. the spread type and amount are configured via select pin. using idt?s patented phase-locked loop (pll) techniques, the device takes a 25 mhz crystal input and produces two pairs of differential outputs at 25 mhz, 100 mhz, 125 mhz or 200 mhz clock frequencies for hcsl, and 25 mhz or 100 mhz for lvds. features ? packaged in 16-pin tssop ? available in rohs 5 (green) or rohs 6 (green and lead free) compliant packaging ? supports hcsl or lvds output levels ? operating voltage of 3.3 v ? input frequency of 25 mhz ? jitter 80 ps (peak-to-peak) ? spread spectrum capability ? industrial and commercial temperature ranges block diagram phase lock loop clock buffer/ crystal oscillator vdd gnd x1/iclk x2 25 mhz crystal or clock control logic ss1:ss0 2 s1:s0 2 clk0 clk0 rr(iref) clk1 clk1 2 2 oe optional tuning crystal capacitors
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 2 ics557-03 rev l 022608 pin assignment output select table 1 (mhz) spread selection table 2 pin descriptions 1 2 3 x2 4 s1 5 6 clk0 7 8 clk0 gndoda vddxd oe ss0 16 x1/iclk ss1 clk1 vddoda 15 14 13 12 11 10 9 16-pin (173 mil) tssop gndxd s0 iref clk1 s1 s0 clk(1:0), clk(1:0) 00 25m 0 1 100m 1 0 125m 1 1 200m ss1 ss0 spread% 00 no spread 0 1 down -0.5 1 0 down -0.75 11 no spread pin number pin name pin type pin description 1 s0 input select pin 0. see table1. internal pull-up resistor. 2 s1 input select pin 1. see table 1. internal pull-up resistor. 3 ss0 input spread select pin 0. see table 2. internal pull-up resistor. 4 x1/iclk input crystal or clock input. connect to a 25 mhz crystal or single ended clock. 5 x2 output crystal connection. leave unconnected for clock input. 6 oe input output enable. tri-states outputs and device is not shut down. internal pull-up resistor. 7 gndxd power connect to ground. 8 ss1 input spread select pin 1. see table 2. internal pull-up resistor. 9 iref output precision resistor attached to this pin is connected to the internal current reference. 10 clk1 output hcsl complimentary clock output 1. 11 clk1 output hcsl true clock output 1. 12 vddoda power connect to voltage supply +3.3 v for output driver and analog circuits 13 gndoda power connect to ground. 14 clk0 output hcsl complimentary clock output 0. 15 clk0 output hcsl true clock output 0. 16 vddxd power connect to voltage supply +3.3 v for crystal oscillator and digital circuit.
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 3 ics557-03 rev l 022608 applications information external components a minimum number of external components are required for proper operation. decoupling capacitors decoupling capacitors of 0.01 f should be connected between each vdd pin and the ground plane, as close to the vdd pin as possible. do not share ground vias between components. route power from power source through the capacitor pad and then into ics pin. crystal a 25 mhz fundamental mode parallel resonant crystal should be used. this crystal must have less than 300 ppm of error across temperature in order for the ics557-03 to meet pci express specifications. crystal capacitors crystal capacitors are connected from pins x1 to ground and x2 to ground to optimize the accuracy of the output frequency. c l = crystal?s load capacitance in pf crystal capacitors (pf) = (c l - 8) * 2 for example, for a crystal with a 16 pf load cap, each external crystal cap would be 16 pf. (16-8)*2=16. current source (iref) reference resistor - r r if board target trace impedance (z) is 50 ? , then r r = 475 ? (1%), providing iref of 2.32 ma. the output current (i oh ) is equal to 6*iref. output termination the pci-express differential clock outputs of the ics557-03 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the ics557-03 can also be configured for lvds compatible voltage levels. see the lvds compatible layout guidelines section. output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the ics557-03.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5 ?
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 4 ics557-03 rev l 022608 pci-express layout guidelines pci-express device routing typical pci-express (hcsl) waveform common recommendations for differential routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch l3 length, route as non-coupled 50 ohm trace. 0.2 max inch r s 33 ohm r t 49.9 ohm differential routing on a single pcb dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch differential routing to a pci express connector dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch r s r s r t r t pci-express load or connector l1 l2 l3? l4 l1? l2? l3 l4? ics557-03 output clock 0.175 v 0.525 v 0.175 v 0.525 v t or t of 500 ps 500 ps 700 mv 0
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 5 ics557-03 rev l 022608 lvds compatible layout guidelines lvds device routing typical lvds waveform lvds recommendations fo r differential routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch r p 100 ohm r q 100 ohm r t 150 ohm l1 l2? l3 l1? l2 l3? r q r p lvds device load ics557-03 clock output r t r t 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 6 ics557-03 rev l 022608 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics557-03. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificat ions is not implied. exposure to ab solute maximum rating conditions for extended periods can affect product reliability. electrical parameters are gua ranteed only over the recommended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v 10% , ambient temperature -40 to +85 c 1. single edge is monotonic when transitioning through region. 2. inputs with pull-ups/-downs are not included. item rating supply voltage, vddxd, vddoda 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c esd protection (input) 2000 v min. (hbm) parameter symbo l conditions min. typ. max. units supply voltage v 2.97 3.3 3.63 v input high voltage 1 v ih s0, s1, oe, iclk, ss0, ss1 2.0 vdd +0.3 v input low voltage 1 v il s0, s1, oe, iclk, ss0, ss1 vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 a operating supply current i dd 50 ? , 2 pf 78 ma i ddoe oe =low 44 ma input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf pin inductance l pin 5nh output resistance r out clk outputs 3.0 k ? pull-up resistor r pu s0, s1, oe, ss0, ss1 100 k ?
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 7 ics557-03 rev l 022608 ac electrical characterist ics - clk0/clk1, clk0/clk1 unless stated otherwise, vdd=3.3 v 10% , ambient temperature -40 to +85 c note 1: test setup is r l =50 ohms with 2 pf, rr = 475 ? (1%). note 2: measurement taken from a single-ended waveform. note 3: measurement taken from a differential waveform. note 4: measured at the crossing point where instantaneous voltages of both clk and clk are equal. note 5: clk pins are tri-stated when oe is low as serted. clk is driven diff erential when oe is high. parameter symbol conditions min. typ. max. units input frequency 25 mhz output frequency hcsl termination 25 200 mhz lvds termination 25 100 mhz output high voltage 1,2 v oh hcsl 660 700 850 mv output low voltage 1,2 v ol hcsl -150 0 27 mv crossing point voltage 1,2 absolute 250 350 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 80 ps frequency synthesis error all outputs 0 ppm modulation frequency spread spectrum 30 31.5 33 khz rise time 1,2 t or from 0.175 v to 0.525 v 175 332 700 ps fall time 1,2 t of from 0.525 v to 0.175 v 175 344 700 ps rise/fall time variation 1,2 125 ps output to output skew 50 ps duty cycle 1,3 45 55 % output enable time 5 all outputs 10 12 s output disable time 5 all outputs 10 12 s stabilization time t stable from power-up vdd=3.3 v 3.0 3.5 ms spread spectrum transition time t spread stabilization time after spread spectrum changes 3.0 3.5 ms
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 8 ics557-03 rev l 022608 thermal characteristics marking diagram (ics557g-03) marking diagram (ics557g-03lf) marking diagram (ics557gi-03) marking diagram (ics557gi-03lf) notes: 1. ###### is the lot code. 2. yyww is the last two digits of the year, and the week number that the part was assembled. 3. ?lf? designates pb (lead) free package. 4. ?i? deisgnates industrial temperature range. 5. bottom marking: (origin). origin = country of origin of not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w 8 16 9 557g-03 ###### yyww$$ 1 8 16 9 557g03lf ###### yyww 1 8 16 9 557gi-03 ###### yyww$$ 1 8 16 9 557gi03l ###### yyww 1
ics557-03 pci-express clock source pcie sscg idt? / ics? pci-express clock source 9 ics557-03 rev l 022608 package outline and package dimensions (16-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a ?lf? suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature ics557g-03 see page 8 tubes 16-pin tssop 0 to +70 c ics557g-03t tape and reel 16-pin tssop 0 to +70 c ics557g-03lf tubes 16-pin tssop 0 to +70 c ICS557G-03LFT tape and reel 16-pin tssop 0 to +70 c ics557gi-03 see page 8 tubes 16-pin tssop -40 to +85 c ics557gi-03t tape and reel 16-pin tssop -40 to +85 c ics557gi-03lf tubes 16-pin tssop -40 to +85 c ics557gi-03lft tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a1 a a2 e - c - b aaa c c l millimeters inches* symbol min max min max a -- 1.20 -- 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 a0 8 0 8 aaa -- 0.10 -- 0.004
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com ics557-03 pci-express clock source pcie sscg
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